1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular, to a semiconductor memory device to be applied to a memory cell array of a dynamic random-access memory (DRAM).
2. Description of the Prior Art
Conventionally, a DRAM includes a memory cell array constituted with, for example, a first plate 10a and a second plate 10b as shown in FIG. 4. The plates 10a and 10b respectively include portions of the memory cell array. In the plate 10a, word lines WL0 to WL2n-1 and bit lines BL0 to BLm-1 and BL0 to BLm-1 are arranged to intersect each other. Moreover, a sense amplifier group 12a and row decoder 14a are disposed therein. Similarly, the plate 10b includes word lines WL0 to WL2n-1, bit lines BLm to BL2m-1 and BLm to BL2m-1 which are arranged to intersect each other, a sense amplifier group 12b, and a row decoder 14b.
Each of the sense amplifier groups 12a and 12b is constituted with m sense amplifiers 0 to m-1 and m to 2m-1, whereas each of the row decoders 14a and 14b is disposed to drive word lines WL0 to WL2n-1. At each intersection between the word lines WL0 to WL2n-1 and the bit lines BL0 to BL2m-1 and BL0 to BL2m-1, there is formed a memory cell MC, which comprises a transistor and a capacitor. The sense amplifier groups 12a and 12b each are supplied with a sense amplifier activation signal .phi..sub.A and a bit likne precharge balance signal .phi..sub.P. In the memory device shown in FIG. 4, since the memory cells MCs are arranged in a 2n (rows).times.m(columns) array in each of the plates 10a and 10b, the memory device includes a total of 2n(rows).times.2m(columns) memory cells MCs.
Referring now to a signal timing chart of FIG. 5, description will be given of a case where the memory cells are refreshed, for example, in a first row of the memory cell array.
When a row address strobe signal RAS is activated or enabled, the bit precharge balance signal .phi..sub.P is first set to a low level, which terminates a precharge operation on the bit lines. Next, the row decoders 14a and 14b respectively select two word lines WL0 and WL0 in the plates 10a and 10b, respectively, thereby setting these word lines to a high level. As a result, information is transmitted from the memory cells MC of the first row thus selected to the bit line BL0 and BLm. Assuming now that a memory cell MC representatively denoted by a solid circle at a cross-point between the word line WL0 and the bit line BL0 is loaded with "low" data at a low level, the level of the bit line BL0 is slightly decreased, leading to a potential difference .DELTA.V1 between the bit line BL0 and the bit line BL0 kept retained at a reference level V.sub.R.
After the memory cell information is transmitted to the bit line, when a sense amplifier activation signal .phi..sub.A is supplied to and activates the sense amplifier groups 12a and 12b, the initial potential difference .DELTA.V1 between bit lines appearing between the bit lines BL0 and BL0 is amplified up to a level (Vcc-GND). When the sense operation is finished, the word line WL0 is restored to a low level and thereafter when the bit line precharge balance signal .phi..sub.P is again set to a high level, the bit lines BL0 and BL0 are returned to the reference level V.sub.R. Through the sequence of operations above, the 2m memory cells thus selected are completely refreshed.
Let us assume that the reference level V.sub.R of each bit line in a holding state is set to Vcc/2. Under this condition, when a memory cell refreshing operation is achieved, memory cell charge and discharge operations are conducted through the bit lines, causing the following current. EQU I=2m.multidot.C.sub.D .multidot.Vcc/(2.multidot.Tcyc) (1)
where, C.sub.D is a bit line capacity and Tcyc denotes refresh cycle time. Most portions of the current appearing in a DRAM are occupied by the charge/discharge current flowing through the bit lines as represented by the expression (1). As can be appreciated from this expression, the current is proportional to the bit line capacity C.sub.D and the number 2m of sense amplifiers simultaneously selected. In consequence, the conventional memory device has a problem that when the memory capacity becomes larger, the current becomes greater in proportion to an increase in the number of pairs of bit lines associated with the increase in the memory capacity.